In this application, we have applied tiberCAD to 3D calculations of electrical characteristics of a Si-based 3-gate FinFET device.

For the last years, three-dimensional Multi-gate FET devices (double, triple or quadruple-gate) have been evolving from the silicon-on-insulator (SOI) classical, planar single gate MOSFET, in order to satisfy increasing need for higher current drive and better short channel behaviour.

The first fully depleted SOI MOSFET (early 1980's) showed superior transconductance, current drive and subthreshold swing. Its development led to the double-gate SOI MOSFET, which provided good short-channel characteristics due to the better gate control on the channel. A natural evolution of the latter was the vertical-channel double-gate FinFET. Triple-gate and gate-all-around implementations of the FinFET structure followed shortly. The phenomenon of volume inversion, leading to large transconductance, has encouraged the development of a series of these structures, ranging from quantum-wire MOSFET to circular section surrounding-gate devices with a pillar-like silicon island and vertical channel.

We consider here a three-gate FinFET structure with a 20 nm thick and 40 nm high Silicon fin. The channel length is 50 nm and the gate oxide thickness is 2 nm; we will see in the following the effects of the scaling of the device.

Here is the geometrical description of the Finfet device (left) and how it is meshed by GMSH (right). In the middle, particular of the fin surrounded by the gate oxide.

DEVICE STRUCTURE

The model of the Finfet structure in tiberCAD is composed by these regions:

• Silicon Fin region, with a very low doping:
• Polysilicon gate region, highly doped
• Source and Drain contact region, highly doped:
• Gate oxide (SiO₂) region

A drift-diffusion simulation has been performed on the Finfet model.
First, a 50n-channel Finfet has been considered.

Electron Charge density in the fin for Vd = 1 and
Vg = 0.5
The volume inversion inside the fin is visible, as well as the pinch off towards the source contact.                                                        Clip of the electron density in the fin, close to the drain contact region.

Electron density in the fin for Vg = 0.5 and Vd = 1.
A full inversion is present inside the channel, with a pinch-off towards the drain contact region.                                                        Electron density in the fin, for Vg = -0.3 and Vd = 1.
In the subthreshold regime, no inversion and no electron charge is present inside the channel.

IV CHARACTERISTICS

IV drain output characteristics for a 50 nm channel length. Threshold voltage is around Vg = -0.3V
Drain current ouput level is around 5x10^-6 A for Vg = 0                                                      Id/Vg Transcharacteristic with Vd = 1V, for 50 nm channel length

The subthreshold S parameter, given by , in this case is 75 mV/dec.

SCALING OF THE CHANNEL LENGTH

Drain characteristics for channel length ranging from 5 to 100 nm

It can be noted that, for this set of geometrical parameters, scaling channel lengths below 20 nm results in bad gate control on the channel current.
To avoid short channel effects it is necessary to scale down Silicon fin thickness and/or gate oxide thickness.

Id/Vg Transfer characteristics for channel length ranging from 5 to 100 nm

Again, It is clear that, for channel lengths below 20 nm, scaling leads to a bad subthreshold behaviour, due to short channel effects.
S parameter in this case range from 61 to 250 mv/dec and more.

Silicon Fin length/thickness ratio dependence of subthreshold parameter S

Only for channel length 3-4 times larger than the fin thickness (20 nm in this example), scaling rules are correctly fulfilled and S parameter has a reasonably low value (60-80).

Short channel effects can be avoided by reducing the fin thickness (W_Si) or even by reducing the gate oxide thickness (t_Ox), so that the natural length parameter lambda is improved. Lambda can be reduced also by increasing the number n of gates or by increasing the gate oxide dielectric constant (if high-k oxides are used); in this case the physical oxide thickness can be increased, limiting the tunneling leakage.

SCALING OF THE OXIDE THICKNESS

By reducing oxide thickness from 2 nm to 1 nm, it is possible to improve short channel performances significantly.

Effect on subthreshold transfer characterisctics, for channel lengths from 5 to 20 nm

Scaling oxide from 2 to 1 nm improves S parameter from 170 to 100 mV/dec for 20 nm channel.
For shorter lengths the slope is better, too, even if one must remember that, for less than 10 nm-long channels, quantum effects (not considered here) become a critical issue.

Moreover, gate oxide thickness values lower than 2 nm lead to serious tunneling leakage levels, which poses a strict limitation on further scaling, if SiO₂ is to be used as gate oxide.

The solution to this issue presently mostly investigated in Si MOSFET technology is the substitution of SiO₂ with alternative high-k oxide, such as HfO₂, which can yield an equivalent oxide thickness lower than 1 nm, still keeping tunneling leakage low with a larger physical thickness.

References

• S.Casaluci, "Simulazione di dispositivi FinFET", thesis, 2008
• Jakub Kedzierski, David M. Fried, Edward J. Nowak, "Hight-performance symmetric-gate and CMOS-compatible V_t asymmetric-gate FinFET device", IEDM 2001
• Jean-Pierre Coline, Multiple-gate SOI MOSFETs, Solid-State Electronics, 48 (2004), 897–905